After configuration setting of a circuit in a field programmable gate array (FPGA), design of a semiconductor integrated circuit, or the like is carried out, timing analysis for checking whether the circuit correctly operates at a clock frequency requested by the designer is carried out. The FPGA is a form of integrated circuits inside which a desired circuit configuration may be set by a purchaser or designer after manufacturing, for example.
As a method for setting a circuit configuration in an FPGA, there is a technique that a netlist in which functions of the target circuit of the design are described is logically synthesized by using a hardware description language and layout is carried out for the FPGA based on the gate-level netlist obtained by the logic synthesis.
Furthermore, in design of a semiconductor integrated circuit, register transfer level (RTL) design, layout design, and so forth are carried out. In the RTL design, user specifications are converted to a description of the register transfer level. In the RTL design, how the respective parts of the semiconductor integrated circuit behave every clock cycle is described in a netlist or the like by a hardware description language or the like. In the layout design, layout is carried out based on a gate-level netlist obtained by logically synthesizing the RTL netlist.
As a related art, there is a technique in which, for example, operation by a designer from the start of design work to the end is recorded and the level of proficiency of the designer in the design is determined based on the degree of change in the number of errors detected by a design rule check with respect to the elapsed time of the design (for example, refer to Japanese Laid-open Patent Publication No. 2012-58911).
Furthermore, as a related art, for example, there is a technique in which a timing constraints file implemented in a downstream process after layout is extracted based on the result of clock domain crossing (CDC) verification carried out in an upstream process in development of a semiconductor integrated circuit (for example, refer to Japanese Laid-open Patent Publication No. 2012-168718).
However, for example, it is difficult to analyze timing errors obtained by timing analysis and identify the causes of the timing errors. For example, identifying the causes of timing errors is carried out based on the experience of the verifier and therefore is difficult depending on the level of proficiency of the verifier. Furthermore, for example, if the number of timing errors is large, it is difficult to analyze all timing errors at a time. Thus, the timing errors are divided into plural groups and many times of analysis are carried out. Therefore, the analysis takes a long time.
In one aspect, the embodiment discussed herein aims at providing a verification support program, a verification support method, and an information processing device that may intend to improve the efficiency of analysis of timing errors.